Role Number: 200438203

• Deep knowledge of System Verilog test-bench language and UVM
• Validated experience developing scalable and portable test-benches
• Validated experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
• Experience with IP verification methodology
• In lieu of UVM knowledge, C/C++ authority knowledge
• Significant experience with DDR PHY or Controller
• Deep knowledge of one of the scripting languages: Python, Perl, TCL
• Deep knowledge of formal verification methodology

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to the following: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP designs.

BS degree in technical discipline with minimum 3 years of relevant experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.